PCILMR(8) | The PCI Utilities | PCILMR(8) |
pcilmr - margin PCIe Links
pcilmr [--margin] [<margining
options>] <downstream component> ...
pcilmr --full [<margining options>]
pcilmr --scan
List of the requirements for links and system settings to run the margining test.
BIOS settings (depends on the system, relevant for server baseboards with Xeon CPUs):
Device (link) requirements:
pcilmr utility allows you to take advantage of the PCIe Lane Margining at the Receiver capability which is mandatory for all Ports supporting a data rate of 16.0 GT/s or higher, including Pseudo Ports (Retimers). Lane Margining at Receiver enables system software to obtain the margin information of a given Receiver while the Link is in the L0 state. The margin information includes both voltage and time, in either direction from the current Receiver position. Margining support for timing is required, while support for voltage is optional at 16.0 GT/s and required at 32.0 GT/s and higher data rates. Also, independent time margining and independent voltage margining is optional.
Utility allows to get an approximation of the eye margin diagram in the form of a rhombus (by four points). Lane Margining at the Receiver capability enables users to margin PCIe links without a hardware debugger and without the need to stop the target system. Utility can be useful to debug link issues due to receiver margins.
However, the utility results may be not particularly accurate and, as it was found out during testing, specific devices provide rather dubious capability support and the reliability of the information they provide is questionable. The PCIe specification provides reference values for the eye diagram, which are also used by the pcilmr to evaluate the results, but it seems that it makes sense to contact the manufacturer of a particular device for references.
The PCIe Base Specification Revision 5.0 sets allowed range for Timing Margin from 20% UI to 50% UI and for Voltage Margin from 50 mV to 500 mV. Utility uses 30% UI as the recommended value for Timing - taken from NVIDIA presentation ("PCIe 4.0 Mass Electrical Margins Data Collection").
pcilmr requires root privileges (to access Extended Configuration Space), but during our testing there were no problems with the devices and they successfully returned to their normal initial state after the end of testing.
<device/component> [<domain>:]<bus>:<dev>.<func> (see lspci(8))
Use only one of -T/-t options at the same time (same for
-V/-v).
Without these options utility will use MaxSteps from Device
capabilities as test limit.
Utility syntax example:
lspci(8), PCI Express Base Specification (Lane Margining at Receiver)
25 February 2024 | pciutils-3.11.1 |