JKT_EVENTS(3CPC) CPU Performance Counters Library Functions JKT_EVENTS(3CPC)

jkt_events — processor model specific performance counter events

This manual page describes events specific to the following Intel CPU models and is derived from Intel's perfmon data. For more information, please consult the Intel Software Developer's Manual or Intel's perfmon website.

CPU models described by this document:

The following events are supported:

Not taken macro-conditional branches.
Taken speculative and retired macro-conditional branches.
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.
Taken speculative and retired indirect branches excluding calls and returns.
Taken speculative and retired indirect branches with return mnemonic.
Taken speculative and retired direct near calls.
Taken speculative and retired indirect calls.
Speculative and retired macro-conditional branches.
Speculative and retired macro-unconditional branches excluding calls and indirects.
Speculative and retired indirect branches excluding calls and returns.
Speculative and retired indirect return branches.
Speculative and retired direct near calls.
Not taken speculative and retired mispredicted macro conditional branches.
Taken speculative and retired mispredicted macro conditional branches.
Taken speculative and retired mispredicted indirect branches excluding calls and returns.
Taken speculative and retired mispredicted indirect branches with return mnemonic.
Taken speculative and retired mispredicted direct near calls.
Taken speculative and retired mispredicted indirect calls.
Speculative and retired mispredicted macro conditional branches.
Mispredicted indirect branches excluding calls and returns.
Speculative and retired mispredicted direct near calls.
Thread cycles when thread is not in halt state.
Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.
This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.
Number of Uops delivered by the LSD.
Cycles Uops delivered by the LSD, but didn't come from the decoder.
Stalls caused by changing prefix length of the instruction.
Stall cycles because IQ is full.
Valid instructions written to IQ per cycle.
Instruction Decode Queue (IDQ) empty cycles.
Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.
Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.
This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
Decode Stream Buffer (DSB)-to-MITE switches.
This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.
Cases of cancelling valid DSB fill not because of exceeding way limit.
Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.
Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.
Increments the number of flags-merge uops in flight each cycle.
This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.
Multiply packed/scalar single precision uops allocated.
Resource-related stall cycles.
Counts the cycles of stall due to lack of load buffers.
Cycles stalled due to no eligible RS entry available.
Cycles stalled due to no store buffers available. (not including draining form sync).
Cycles stalled due to re-order buffer full.
Cycles when Allocator is stalled if BOB is full and new branch needs it.
This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.
Cycles when Reservation Station (RS) is empty for the thread.
Unhalted core cycles when the thread is in ring 0.
Number of intervals between processor halts while thread is in ring 0.
Unhalted core cycles when thread is in rings 1, 2, or 3.
Count cases of saving new LBR.
This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.
This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.
Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.
Number of instructions retired. General Counter - architectural event.
This event counts the number of micro-ops retired.
This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.
Cycles without actually retired uops.
Cycles with less than 10 actually retired uops.
Conditional branch instructions retired.
Direct and indirect near call instructions retired.
All (macro) branch instructions retired.
Return instructions retired.
Not taken branch instructions retired.
Taken branch instructions retired.
Far branch instructions retired.
All (macro) branch instructions retired. (Precise Event - PEBS).
Mispredicted conditional branch instructions retired.
Direct and indirect mispredicted near call instructions retired.
All mispredicted macro branch instructions retired.
Mispredicted not taken branch instructions retired.
Mispredicted taken branch instructions retired.
Mispredicted macro branch instructions retired. (Precise Event - PEBS)
Retired instructions experiencing ITLB misses.
Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.
Number of transitions from AVX-256 to legacy SSE when penalty applicable.
Number of transitions from SSE to AVX-256 when penalty applicable.
Number of X87 assists due to output value.
Number of X87 assists due to input value.
Number of SIMD FP assists due to Output values.
Number of SIMD FP assists due to input values.
Retired load uops that miss the STLB.
Retired store uops that miss the STLB.
Retired load uops with locked access.
This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts the number of load uops retired
This event counts the number of store uops retired.
Retired load uops with L1 cache hits as data sources.
Retired load uops with L2 cache hits as data sources.
This event counts retired load uops that hit in the last-level (L3) cache without snoops required.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.
Retired load uops which data sources were hits in LLC without snoops required.
Data from local DRAM either Snoop not needed or Snoop Miss (RspI)
Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)
Cycles when divider is busy executing divide operations.
This event counts the number of the divide operations executed.
Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.
Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.
Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.
Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.
Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.
Number of GSSE-256 Computational FP single precision uops issued this cycle.
Number of AVX-256 Computational FP double precision uops issued this cycle.
Uops dispatched per thread.
Uops dispatched from any thread.
Cycles per thread when uops are dispatched to port 0.
Cycles per thread when uops are dispatched to port 1.
Cycles per thread when uops are dispatched to port 4.
Cycles per thread when uops are dispatched to port 5.
Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.
Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.
Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.
Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
Misses at all ITLB levels that cause page walks.
Misses in all ITLB levels that cause completed page walks.
This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.
Operations that miss the first ITLB level but hit the second and do not cause any page walks.
Load misses in all DTLB levels that cause page walks.
Load misses at all DTLB levels that cause completed page walks.
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.
This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.
Store misses in all DTLB levels that cause page walks.
Store misses in all DTLB levels that cause completed page walks.
Cycles when PMH is busy with page walks.
Store operations that miss the first TLB level but hit the second and do not cause page walks.
DTLB flush attempts of the thread-specific entries.
STLB flush attempts.
This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.
Allocated L1D data cache lines in M state.
L1D data cache lines in M state evicted due to replacement.
Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.
L1D miss oustandings duration in cycles.
Cycles with L1D load Misses outstanding.
Not software-prefetch load dispatches that hit FB allocated for software prefetch.
Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.
Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .
Cycles when L1 and L2 are locked due to UC or split lock.
Cycles when L1D is locked.
Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.
This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.
This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).
Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.
This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
Speculative cache line split load uops dispatched to L1 cache.
Speculative cache line split STA uops dispatched to L1 cache.
This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.
Offcore outstanding Demand Data Read transactions in uncore queue.
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.
Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.
Demand Data Read requests sent to uncore.
Cacheable and noncachaeble code read requests.
Demand RFO requests including regular RFOs, locks, ItoM.
Demand and prefetch data reads.
Cases when offcore requests buffer cannot take more entries for core.
Demand Data Read requests that hit L2 cache.
RFO requests that hit L2 cache.
RFO requests that miss L2 cache.
L2 cache hits when fetching instructions, code reads.
L2 cache misses when fetching instructions.
Requests from the L2 hardware prefetchers that hit L2 cache.
Requests from the L2 hardware prefetchers that miss L2 cache.
RFOs that miss cache lines.
RFOs that hit cache lines in E state.
RFOs that hit cache lines in M state.
RFOs that access cache lines in any state.
Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).
Not rejected writebacks from L1D to L2 cache lines in S state.
Not rejected writebacks from L1D to L2 cache lines in E state.
Not rejected writebacks from L1D to L2 cache lines in M state.
Not rejected writebacks from L1D to L2 cache lines in any state.
Demand Data Read requests that access L2 cache.
RFO requests that access L2 cache.
L2 cache accesses when fetching instructions.
L2 or LLC HW prefetches that access L2 cache.
L1D writebacks that access L2 cache.
L2 fill requests that access L2 cache.
L2 writebacks that access L2 cache.
Transactions accessing L2 pipe.
L2 cache lines in I state filling L2.
L2 cache lines in S state filling L2.
L2 cache lines in E state filling L2.
This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.
Clean L2 cache lines evicted by demand.
Dirty L2 cache lines evicted by demand.
Clean L2 cache lines evicted by L2 prefetch.
Dirty L2 cache lines evicted by L2 prefetch.
Dirty L2 cache lines filling the L2.
Core-originated cacheable demand requests missed LLC.
Core-originated cacheable demand requests that refer to LLC.
Split locks in SQ.
Reference cycles when the thread is unhalted (counts at 100 MHz rate).
Count XClk pulses when this thread is unhalted and the other is halted.
Cycles per core when uops are dispatched to port 0.
Cycles per core when uops are dispatched to port 1.
Cycles per core when uops are dispatched to port 4.
Cycles per core when uops are dispatched to port 5.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
Cycles per thread when load or STA uops are dispatched to port 2.
Cycles per thread when load or STA uops are dispatched to port 3.
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.
Cycles per core when load or STA uops are dispatched to port 2.
Cycles per core when load or STA uops are dispatched to port 3.
Demand Data Read requests.
RFO requests to L2 cache.
L2 code requests.
Requests from L2 hardware prefetchers.
Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.
Resource stalls2 control structures full for physical registers.
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Cycles with either free list is empty.
Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.
Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.
Resource stalls out of order resources full.
Resource stalls due to load or store buffers all being in use.
Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.
Cycles when 1 or more uops were delivered to the by the front end.
Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).
Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.
Cycles Decode Stream Buffer (DSB) is delivering any Uop.
Cycles MITE is delivering 4 Uops.
Cycles MITE is delivering any Uop.
Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.
Cycles with any input/output SSE or FP assist.
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Speculative and retired branches.
Speculative and retired mispredicted macro conditional branches.
Uops delivered to Instruction Decode Queue (IDQ) from MITE path.
Cycles without actually retired uops.
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
Number of machine clears (nukes) of any type.
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
Core cycles when at least one thread on the physical core is not in halt state.
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
Cycles at least 1 micro-op is executed from any thread on physical core.
Cycles at least 2 micro-op is executed from any thread on physical core.
Cycles at least 3 micro-op is executed from any thread on physical core.
Cycles at least 4 micro-op is executed from any thread on physical core.
Cycles with no micro-ops executed from any thread on physical core.
Cycles with L1D load Misses outstanding from any thread on physical core.
Cycles a demand request was blocked due to Fill Buffers inavailability.
Reference cycles when the thread is unhalted (counts at 100 MHz rate)
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
Count XClk pulses when this thread is unhalted and the other thread is halted.

cpc(3CPC)

https://download.01.org/perfmon/index/

June 18, 2018 OmniOS