IVT_EVENTS(3CPC) CPU Performance Counters Library Functions IVT_EVENTS(3CPC)

ivt_events — processor model specific performance counter events

This manual page describes events specific to the following Intel CPU models and is derived from Intel's perfmon data. For more information, please consult the Intel Software Developer's Manual or Intel's perfmon website.

CPU models described by this document:

The following events are supported:

Loads blocked by overlapping with store buffer that cannot be forwarded.
The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
Speculative cache-line split load uops dispatched to L1D.
Speculative cache-line split Store-address uops dispatched to L1D.
False dependencies in MOB due to partial compare on address.
Misses in all TLB levels that cause a page walk of any page size from demand loads.
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
Misses in all TLB levels that caused page walk completed of any size by demand loads.
Demand load cycles page miss handler (PMH) is busy with this walk.
Cycle PMH is busy with a walk due to demand loads.
Page walk for a large page completed for Demand load.
Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)
Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.
Number of flags-merge uops allocated. Such uops adds delay.
Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
Number of multiply packed/scalar single precision uops allocated.
Counts number of X87 uops executed.
Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.
Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.
Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.
Counts number of SSE* or AVX-128 double precision FP scalar uops executed.
Counts 256-bit packed single-precision floating-point instructions.
Counts 256-bit packed double-precision floating-point instructions.
Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.
Divide operations executed.
Demand Data Read requests that hit L2 cache.
Counts any demand and L1 HW prefetch data load requests to L2.
RFO requests that hit L2 cache.
Counts the number of store RFO requests that miss the L2 cache.
Counts all L2 store RFO requests.
Number of instruction fetches that hit the L2 cache.
Number of instruction fetches that missed the L2 cache.
Counts all L2 code requests.
Counts all L2 HW prefetcher requests that hit L2.
Counts all L2 HW prefetcher requests that missed L2.
Counts all L2 HW prefetcher requests.
RFOs that miss cache lines.
RFOs that hit cache lines in M state.
RFOs that access cache lines in any state.
Not rejected writebacks that missed LLC.
Not rejected writebacks from L1D to L2 cache lines in E state.
Not rejected writebacks from L1D to L2 cache lines in M state.
Not rejected writebacks from L1D to L2 cache lines in any state.
This event counts each cache miss condition for references to the last level cache.
This event counts requests originating from the core that reference a cache line in the last level cache.
Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.
Core cycles when at least one thread on the physical core is not in halt state.
Increments at the frequency of XCLK (100 MHz) when not halted.
Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)
Reference cycles when the thread is unhalted. (counts at 100 MHz rate)
Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)
Count XClk pulses when this thread is unhalted and the other is halted.
Count XClk pulses when this thread is unhalted and the other thread is halted.
Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.
Cycles with L1D load Misses outstanding.
Cycles with L1D load Misses outstanding from any thread on physical core.
Cycles a demand request was blocked due to Fill Buffers inavailability.
Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).
Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).
Cycles PMH is busy with this walk.
Store operations that miss the first TLB level but hit the second and do not cause page walks.
Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
Counts the number of lines brought into the L1 data cache.
Number of integer Move Elimination candidate uops that were eliminated.
Number of SIMD Move Elimination candidate uops that were eliminated.
Number of integer Move Elimination candidate uops that were not eliminated.
Number of SIMD Move Elimination candidate uops that were not eliminated.
Unhalted core cycles when the thread is in ring 0.
Number of intervals between processor halts while thread is in ring 0.
Unhalted core cycles when the thread is not in ring 0.
Cycles the RS is empty for the thread.
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
Counts load operations that missed 1st level DTLB but hit the 2nd level.
Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.
Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.
Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.
Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
Cycles in which the L1D is locked.
Counts cycles the IDQ is empty.
Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.
Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.
Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.
Counts cycles DSB is delivered four uops. Set Cmask = 4.
Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.
Counts cycles MITE is delivered four uops. Set Cmask = 4.
Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
Number of uops delivered to IDQ from any path.
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.
Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.
Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.
Misses in all ITLB levels that cause page walks.
Misses in all ITLB levels that cause completed page walks.
Cycle PMH is busy with a walk.
Number of cache load STLB hits. No page walk.
Completed page walks in ITLB due to STLB load misses for large pages.
Stalls caused by changing prefix length of the instruction.
Stall cycles due to IQ is full.
Not taken macro-conditional branches.
Taken speculative and retired macro-conditional branches.
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.
Taken speculative and retired indirect branches excluding calls and returns.
Taken speculative and retired indirect branches with return mnemonic.
Taken speculative and retired direct near calls.
Taken speculative and retired indirect calls.
Speculative and retired macro-conditional branches.
Speculative and retired macro-unconditional branches excluding calls and indirects.
Speculative and retired indirect branches excluding calls and returns.
Speculative and retired indirect return branches.
Speculative and retired direct near calls.
Counts all near executed branches (not necessarily retired).
Not taken speculative and retired mispredicted macro conditional branches.
Taken speculative and retired mispredicted macro conditional branches.
Taken speculative and retired mispredicted indirect branches excluding calls and returns.
Taken speculative and retired mispredicted indirect branches with return mnemonic.
Taken speculative and retired mispredicted indirect calls.
Speculative and retired mispredicted macro conditional branches.
Mispredicted indirect branches excluding calls and returns.
Counts all near executed branches (not necessarily retired).
Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Cycles which a Uop is dispatched on port 0.
Cycles per core when uops are dispatched to port 0.
Cycles which a Uop is dispatched on port 1.
Cycles per core when uops are dispatched to port 1.
Cycles which a Uop is dispatched on port 2.
Uops dispatched to port 2, loads and stores per core (speculative and retired).
Cycles which a Uop is dispatched on port 3.
Cycles per core when load or STA uops are dispatched to port 3.
Cycles which a Uop is dispatched on port 4.
Cycles per core when uops are dispatched to port 4.
Cycles which a Uop is dispatched on port 5.
Cycles per core when uops are dispatched to port 5.
Cycles Allocation is stalled due to Resource Related reason.
Cycles stalled due to no eligible RS entry available.
Cycles stalled due to no store buffers available (not including draining form sync).
Cycles stalled due to re-order buffer full.
Cycles with pending L2 miss loads. Set AnyThread to count per core.
Cycles while L2 cache miss load* is outstanding.
Cycles with pending memory loads. Set AnyThread to count per core.
Cycles while memory subsystem has an outstanding load.
Total execution stalls.
Total execution stalls.
Number of loads missed L2.
Execution stalls while L2 cache miss load* is outstanding.
Execution stalls due to memory subsystem.
Execution stalls while memory subsystem has an outstanding load.
Cycles with pending L1 cache miss loads. Set AnyThread to count per core.
Cycles while L1 cache miss demand load is outstanding.
Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.
Execution stalls while L1 cache miss demand load is outstanding.
Number of Uops delivered by the LSD.
Cycles Uops delivered by the LSD, but didn't come from the decoder.
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.
Number of DSB to MITE switches.
Cycles DSB to MITE switches caused delay.
DSB Fill encountered > 3 DSB lines.
Counts the number of ITLB flushes, includes 4k/2M/4M pages.
Demand data read requests sent to uncore.
Demand code read requests sent to uncore.
Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.
Data read requests sent to uncore (demand and prefetch).
Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.
Counts number of cycles no uops were dispatched to be executed on this thread.
Cycles where at least 1 uop was executed per-thread.
Cycles where at least 2 uops were executed per-thread.
Cycles where at least 3 uops were executed per-thread.
Cycles where at least 4 uops were executed per-thread.
Counts total number of uops to be executed per-core each cycle.
Cycles at least 1 micro-op is executed from any thread on physical core.
Cycles at least 2 micro-op is executed from any thread on physical core.
Cycles at least 3 micro-op is executed from any thread on physical core.
Cycles at least 4 micro-op is executed from any thread on physical core.
Cycles with no micro-ops executed from any thread on physical core.
Cases when offcore requests buffer cannot take more entries for core.
DTLB flush attempts of the thread-specific entries.
Count number of STLB flush attempts.
Number of instructions at retirement.
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.
Number of assists associated with 256-bit AVX store operations.
Number of transitions from AVX-256 to legacy SSE when penalty applicable.
Number of transitions from SSE to AVX-256 when penalty applicable.
Number of times any microcode assist is invoked by HW upon uop writeback.
Retired uops.
Cycles without actually retired uops.
Cycles with less than 10 actually retired uops.
Cycles without actually retired uops.
Retirement slots used.
Number of machine clears (nukes) of any type.
Counts the number of machine clears due to memory order conflicts.
Number of self-modifying-code machine clears detected.
Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
Branch instructions at retirement.
Conditional branch instructions retired.
Direct and indirect near call instructions retired.
Direct and indirect macro near call instructions retired (captured in ring 3).
All (macro) branch instructions retired.
Return instructions retired.
Counts the number of not taken branch instructions retired.
Taken branch instructions retired.
Number of far branches retired.
Mispredicted branch instructions at retirement.
Mispredicted conditional branch instructions retired.
Mispredicted macro branch instructions retired.
number of near branch instructions retired that were mispredicted and taken.
Number of X87 FP assists due to output values.
Number of X87 FP assists due to input values.
Number of SIMD FP assists due to output values.
Number of SIMD FP assists due to input values.
Cycles with any input/output SSE* or FP assists.
Count cases of saving new LBR records by hardware.
Retired load uops that miss the STLB. (Precise Event)
Retired store uops that miss the STLB. (Precise Event)
Retired load uops with locked access. (Precise Event)
Retired load uops that split across a cacheline boundary. (Precise Event)
Retired store uops that split across a cacheline boundary. (Precise Event)
All retired load uops. (Precise Event)
All retired store uops. (Precise Event)
Retired load uops with L1 cache hits as data sources.
Retired load uops with L2 cache hits as data sources.
Retired load uops which data sources were data hits in LLC without snoops required.
Retired load uops which data sources following L1 data-cache miss.
Retired load uops with L2 cache misses as data sources.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
Retired load uops which data sources were HitM responses from shared LLC.
Retired load uops which data sources were hits in LLC without snoops required.
Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).
Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).
Remote cache HITM.
Data forwarded from remote cache.
Number of front end re-steers due to BPU misprediction.
Demand Data Read requests that access L2 cache.
RFO requests that access L2 cache.
L2 cache accesses when fetching instructions.
Any MLC or LLC HW prefetch accessing L2, including rejects.
L1D writebacks that access L2 cache.
L2 fill requests that access L2 cache.
L2 writebacks that access L2 cache.
Transactions accessing L2 pipe.
L2 cache lines in I state filling L2.
L2 cache lines in S state filling L2.
L2 cache lines in E state filling L2.
L2 cache lines filling L2.
Clean L2 cache lines evicted by demand.
Dirty L2 cache lines evicted by demand.
Clean L2 cache lines evicted by the MLC prefetcher.
Dirty L2 cache lines evicted by the MLC prefetcher.
Dirty L2 cache lines filling the L2.
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cpc(3CPC)

https://download.01.org/perfmon/index/

June 18, 2018 OmniOS