BNL_EVENTS(3CPC) CPU Performance Counters Library Functions BNL_EVENTS(3CPC)

bnl_events — processor model specific performance counter events

This manual page describes events specific to the following Intel CPU models and is derived from Intel's perfmon data. For more information, please consult the Intel Software Developer's Manual or Intel's perfmon website.

CPU models described by this document:

The following events are supported:

All store forwards
Good store forwards
Micro-op reissues for any cause
Micro-op reissues for any cause (At Retirement)
Memory references that cross an 8-byte boundary.
Load splits
Store splits
Memory references that cross an 8-byte boundary (At Retirement)
Load splits (At Retirement)
Store splits (Ar Retirement)
ld-op-st splits
Nonzero segbase 1 bubble
Nonzero segbase load 1 bubble
Nonzero segbase store 1 bubble
Nonzero segbase ld-op-st 1 bubble
Number of segment register loads.
Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.
Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.
Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.
Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
L1 hardware prefetch request
Any Software prefetch
Any Software prefetch
Memory accesses that missed the DTLB.
DTLB misses due to load operations.
L0 DTLB misses due to load operations.
DTLB misses due to store operations.
L0 DTLB misses due to store operations
Memory cluster signals to block micro-op dispatch for any reason
Number of page-walks executed.
Duration of page-walks in core cycles
Number of D-side only page walks
Duration of D-side only page walks
Number of I-Side page walks
Duration of I-Side page walks
Floating point computational micro-ops executed.
Floating point computational micro-ops retired.
FXCH uops executed.
FXCH uops retired.
Floating point assists.
Floating point assists for retired operations.
Multiply operations executed.
Multiply operations retired
Divide operations executed.
Divide operations retired
Cycles the divider is busy.
Cycles L2 address bus is in use.
Cycles the L2 cache data bus is busy.
Cycles the L2 transfers data to the core.
L2 cache misses.
L2 cache misses.
L2 cache misses.
L2 cache line modifications.
L2 cache lines evicted.
L2 cache lines evicted.
L2 cache lines evicted.
Modified lines evicted from the L2 cache
Modified lines evicted from the L2 cache
Modified lines evicted from the L2 cache
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 store requests
L2 store requests
L2 store requests
L2 store requests
L2 store requests
L2 locked accesses
L2 locked accesses
L2 locked accesses
L2 locked accesses
L2 locked accesses
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache demand requests from this core that missed the L2
L2 cache demand requests from this core
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Cycles no L2 cache requests are pending
Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions
Number of thermal trips
Core cycles when core is not halted
Bus cycles when core is not halted
L1 Cacheable Data Reads
L1 Cacheable Data Writes
L1 Data reads and writes
L1 Data Cacheable reads and writes
L1 Data line replacements
Modified cache lines allocated in the L1 data cache
Modified cache lines evicted from the L1 data cache
Outstanding cacheable data read bus requests duration.
Outstanding cacheable data read bus requests duration.
Number of Bus Not Ready signals asserted.
Number of Bus Not Ready signals asserted.
Bus cycles when data is sent on the bus.
Bus cycles when data is sent on the bus.
Bus cycles when a LOCK signal is asserted.
Bus cycles when a LOCK signal is asserted.
Bus cycles while processor receives data.
Burst read bus transactions.
Burst read bus transactions.
RFO bus transactions.
RFO bus transactions.
Explicit writeback bus transactions.
Explicit writeback bus transactions.
Instruction-fetch bus transactions.
Instruction-fetch bus transactions.
Invalidate bus transactions.
Invalidate bus transactions.
Partial write bus transaction.
Partial write bus transaction.
Partial bus transactions.
Partial bus transactions.
IO bus transactions.
IO bus transactions.
Deferred bus transactions.
Deferred bus transactions.
Burst (full cache-line) bus transactions.
Burst (full cache-line) bus transactions.
Memory bus transactions.
Memory bus transactions.
All bus transactions.
All bus transactions.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
HIT signal asserted.
HIT signal asserted.
HITM signal asserted.
HITM signal asserted.
Bus queue is empty.
Bus stalled for snoops.
Bus stalled for snoops.
IO requests waiting in the bus queue.
Instruction fetches.
Icache hit
Icache miss
ITLB hits.
ITLB flushes.
ITLB misses.
Cycles during which instruction fetches are stalled.
Decode stall due to PFB empty
Decode stall due to IQ full
All macro conditional branch instructions.
All macro unconditional branch instructions, excluding calls and indirects
All indirect branches that are not calls.
All indirect branches that have a return mnemonic
All non-indirect calls
All indirect calls, including both register and memory indirect.
Only taken macro conditional branch instructions
Mispredicted cond branch instructions retired
Mispredicted ind branches that are not calls
Mispredicted return branches
Mispredicted indirect calls, including both register and memory indirect.
Mispredicted and taken cond branch instructions retired
Non-CISC nacro instructions decoded
CISC macro instructions decoded
All Instructions decoded
SIMD micro-ops executed (excluding stores).
SIMD micro-ops retired (excluding stores).
SIMD saturated arithmetic micro-ops executed.
SIMD saturated arithmetic micro-ops retired.
SIMD packed multiply micro-ops executed
SIMD packed multiply micro-ops retired
SIMD packed shift micro-ops executed
SIMD packed shift micro-ops retired
SIMD packed micro-ops executed
SIMD packed micro-ops retired
SIMD unpacked micro-ops executed
SIMD unpacked micro-ops retired
SIMD packed logical micro-ops executed
SIMD packed logical micro-ops retired
SIMD packed arithmetic micro-ops executed
SIMD packed arithmetic micro-ops retired
Instructions retired (precise event).
Micro-ops retired.
Cycles no micro-ops retired.
Periods no micro-ops retired.
This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.
Self-Modifying Code detected.
Retired branch instructions.
Retired branch instructions that were predicted not-taken.
Retired branch instructions that were mispredicted not-taken.
Retired branch instructions that were predicted taken.
Retired branch instructions that were mispredicted taken.
Retired taken branch instructions.
Retired branch instructions.
Retired mispredicted branch instructions (precise event).
Cycles during which interrupts are disabled.
Cycles during which interrupts are pending and disabled.
Retired Streaming SIMD Extensions (SSE) packed-single instructions.
Retired Streaming SIMD Extensions (SSE) scalar-single instructions.
Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.
Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.
Hardware interrupts received.
Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.
Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.
Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.
Retired loads that hit the L2 cache (precise event).
Retired loads that miss the L2 cache
Retired loads that miss the DTLB (precise event).
SIMD assists invoked.
SIMD Instructions retired.
Saturated arithmetic instructions retired.
Cycles issue is stalled due to div busy.
Branch instructions decoded
Bogus branches
BACLEARS asserted.
Micro-op reissues on a store-load collision
Micro-op reissues on a store-load collision (At Retirement)

cpc(3CPC)

https://download.01.org/perfmon/index/

June 18, 2018 OmniOS