BDX_EVENTS(3CPC) CPU Performance Counters Library Functions BDX_EVENTS(3CPC)

bdx_events — processor model specific performance counter events

This manual page describes events specific to the following Intel CPU models and is derived from Intel's perfmon data. For more information, please consult the Intel Software Developer's Manual or Intel's perfmon website.

CPU models described by this document:

The following events are supported:

This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
- preceding store conflicts with the load (incomplete overlap);
- store forwarding is impossible due to u-arch limitations;
- preceding lock RMW operations are not forwarded;
- store has the no-forward bit set (uncacheable/page-split/masked stores);
- all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.
This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
This event counts speculative cache-line split load uops dispatched to the L1 cache.
This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.
This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.
This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

The following errata may apply to this: BDM69

This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.

The following errata may apply to this: BDM69

This event counts the number of cycles while PMH is busy with the page walk.

The following errata may apply to this: BDM69

Load misses that miss the DTLB and hit the STLB (4K).
Load misses that miss the DTLB and hit the STLB (2M).
Load operations that miss the first DTLB level but hit the second and do not cause page walks.
Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).
This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.
This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).
This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.
Number of flags-merge uops being allocated. Such uops considered perf sensitive
added by GSR u-arch.
Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
Number of Multiply packed/scalar single precision uops allocated.
This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.
This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.
RFO requests that miss L2 cache.
L2 cache misses when fetching instructions.
Demand requests that miss L2 cache.
This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.
All requests that miss L2 cache.
Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.
RFO requests that hit L2 cache.
L2 cache hits when fetching instructions, code reads.
This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.
This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.
This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
This event counts the total number of L2 code requests.
Demand requests to L2 cache.
This event counts the total number of requests from the L2 hardware prefetchers.
All L2 requests.
This event counts the number of WB requests that hit L2 cache.
This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.
This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.
This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.
Core cycles when at least one thread on the physical core is not in halt state.
This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
Reference cycles when the thread is unhalted (counts at 100 MHz rate).
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).
Count XClk pulses when this thread is unhalted and the other thread is halted.
Count XClk pulses when this thread is unhalted and the other thread is halted.
This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.
This event counts duration of L1D miss outstanding in cycles.
Cycles with L1D load Misses outstanding from any thread on physical core.
Cycles a demand request was blocked due to Fill Buffers inavailability.
This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

Store misses in all DTLB levels that cause completed page walks.

The following errata may apply to this: BDM69

This event counts the number of cycles while PMH is busy with the page walk.

The following errata may apply to this: BDM69

Store misses that miss the DTLB and hit the STLB (4K).
Store misses that miss the DTLB and hit the STLB (2M).
Store operations that miss the first TLB level but hit the second and do not cause page walks.
This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.
This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.
This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.
This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.
Number of times a TSX line had a cache conflict.
Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.
Number of times a TSX Abort was triggered due to a non-release/commit store to lock.
Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.
Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.
Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.
Number of times we could not allocate Lock Buffer.
Number of integer Move Elimination candidate uops that were eliminated.
Number of SIMD Move Elimination candidate uops that were eliminated.
Number of integer Move Elimination candidate uops that were not eliminated.
Number of SIMD Move Elimination candidate uops that were not eliminated.
This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.
This event counts when there is a transition from ring 1,2 or 3 to ring0.
This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.
Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.
Unfriendly TSX abort triggered by a vzeroupper instruction.
Unfriendly TSX abort triggered by a nest count that is too deep.
RTM region detected inside HLE.
Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.
This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point.

The following errata may apply to this: BDM76

This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).

The following errata may apply to this: BDM76

Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.

The following errata may apply to this: BDM76

This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

The following errata may apply to this: BDM76

This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

The following errata may apply to this: BDM76

This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

The following errata may apply to this: BDM76

This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

The following errata may apply to this: BDM76

This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

The following errata may apply to this: BDM76

This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.
This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).
This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.
This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.
This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.
This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.
This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.
This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.
This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.
This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.
This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.
This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.
This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.
This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.
This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).
This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.
This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.
This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).
This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

The following errata may apply to this: BDM69

Misses in all ITLB levels that cause completed page walks.

The following errata may apply to this: BDM69

This event counts the number of cycles while PMH is busy with the page walk.

The following errata may apply to this: BDM69

Core misses that miss the DTLB and hit the STLB (4K).
Code misses that miss the DTLB and hit the STLB (2M).
Operations that miss the first ITLB level but hit the second and do not cause any page walks.
This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.
This event counts not taken macro-conditional branch instructions.
This event counts taken speculative and retired macro-conditional branch instructions.
This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.
This event counts taken speculative and retired indirect branches excluding calls and return branches.
This event counts taken speculative and retired indirect branches that have a return mnemonic.
This event counts taken speculative and retired direct near calls.
This event counts taken speculative and retired indirect calls including both register and memory indirect.
This event counts both taken and not taken speculative and retired macro-conditional branch instructions.
This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.
This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.
This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.
This event counts both taken and not taken speculative and retired direct near calls.
This event counts both taken and not taken speculative and retired branch instructions.
This event counts not taken speculative and retired mispredicted macro conditional branch instructions.
This event counts taken speculative and retired mispredicted macro conditional branch instructions.
This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.
This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.
Taken speculative and retired mispredicted indirect calls.
This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.
This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.
This event counts both taken and not taken speculative and retired mispredicted branch instructions.
This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops.
This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.
This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.
Cycles per core when uops are exectuted in port 0.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.
Cycles per core when uops are exectuted in port 1.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.
Cycles per core when uops are dispatched to port 2.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.
Cycles per core when uops are dispatched to port 3.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.
Cycles per core when uops are exectuted in port 4.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.
Cycles per core when uops are exectuted in port 5.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.
Cycles per core when uops are exectuted in port 6.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
Cycles per core when uops are dispatched to port 7.
This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
This event counts resource-related stall cycles.
This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.
This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.
This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.
Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.
Cycles while L2 cache miss demand load is outstanding.
Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).
Cycles while memory subsystem has an outstanding load.
Counts number of cycles nothing is executed on any execution port.
Total execution stalls.
Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.
Execution stalls while L2 cache miss demand load is outstanding.
Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.
Execution stalls while memory subsystem has an outstanding load.
Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.
Cycles while L1 cache miss demand load is outstanding.
Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.
Execution stalls while L1 cache miss demand load is outstanding.
Number of Uops delivered by the LSD.
Cycles Uops delivered by the LSD, but didn't come from the decoder.
This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.
This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).
This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.
This event counts both cacheable and noncachaeble code read requests.
This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.
This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.
This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.
Number of uops to be executed per-thread each cycle.
This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.
Cycles where at least 1 uop was executed per-thread.
Cycles where at least 2 uops were executed per-thread.
Cycles where at least 3 uops were executed per-thread.
Cycles where at least 4 uops were executed per-thread.
Number of uops executed from any thread.
Cycles at least 1 micro-op is executed from any thread on physical core.
Cycles at least 2 micro-op is executed from any thread on physical core.
Cycles at least 3 micro-op is executed from any thread on physical core.
Cycles at least 4 micro-op is executed from any thread on physical core.
Cycles with no micro-ops executed from any thread on physical core.
This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries.
Number of DTLB page walker hits in the L1+FB.

The following errata may apply to this: BDM69, BDM98

Number of DTLB page walker hits in the L2.

The following errata may apply to this: BDM69, BDM98

Number of DTLB page walker hits in the L3 + XSNP.

The following errata may apply to this: BDM69, BDM98

Number of DTLB page walker hits in Memory.

The following errata may apply to this: BDM69, BDM98

Number of ITLB page walker hits in the L1+FB.

The following errata may apply to this: BDM69, BDM98

Number of ITLB page walker hits in the L2.

The following errata may apply to this: BDM69, BDM98

Number of ITLB page walker hits in the L3 + XSNP.

The following errata may apply to this: BDM69, BDM98

This event counts the number of DTLB flush attempts of the thread-specific entries.
This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).
This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).

The following errata may apply to this: BDM61

This is a precise version (that is, uses PEBS) of the event that counts instructions retired.

The following errata may apply to this: BDM11, BDM55

This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.
This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.

The following errata may apply to this: BDM30

This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.

The following errata may apply to this: BDM30

Number of times any microcode assist is invoked by HW upon uop writeback.
This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.
This event counts cycles without actually retired uops.
Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.
This event counts the number of retirement slots used.
This event counts both thread-specific (TS) and all-thread (AT) nukes.
This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer.
This event counts self-modifying code (SMC) detected, which causes a machine clear.
Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.
This event counts all (macro) branch instructions retired.
This event counts conditional branch instructions retired.
This event counts both direct and indirect near call instructions retired.
This event counts both direct and indirect macro near call instructions retired (captured in ring 3).
This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.

The following errata may apply to this: BDW98

This event counts return instructions retired.
This event counts not taken branch instructions retired.
This event counts taken branch instructions retired.
This event counts far branch instructions retired.

The following errata may apply to this: BDW98

This event counts all mispredicted macro branch instructions retired.
This event counts mispredicted conditional branch instructions retired.
This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.
This event counts mispredicted return instructions retired.
Number of near branch instructions retired that were mispredicted and taken.
Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.
Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.
Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.
Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.
Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of times we entered an HLE region
does not count nested transactions.
Number of times HLE commit succeeded.
Number of times HLE abort was triggered.
Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).
Number of times the TSX watchdog signaled an HLE abort.
Number of times a disallowed operation caused an HLE abort.
Number of times HLE caused a fault.
Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.
Number of times we entered an RTM region
does not count nested transactions.
Number of times RTM commit succeeded.
Number of times RTM abort was triggered .
Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).
Number of times the TSX watchdog signaled an RTM abort.
Number of times a disallowed operation caused an RTM abort.
Number of times a RTM caused a fault.
Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.
This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.
This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.
This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.
This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.
This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.
This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.
This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.
This event counts load uops with locked access retired to the architected path.

The following errata may apply to this: BDM35

This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.
This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.
This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.
This event counts retired load uops which data sources were hits in the mid-level (L2) cache.

The following errata may apply to this: BDM35

This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.

The following errata may apply to this: BDM100

This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.
This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.
Miss in last-level (L3) cache. Excludes Unknown data-source.

The following errata may apply to this: BDM100, BDE70

This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.
This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.

The following errata may apply to this: BDM100

This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.

The following errata may apply to this: BDM100

This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).

The following errata may apply to this: BDM100

This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.

The following errata may apply to this: BDM100

Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).

The following errata may apply to this: BDE70, BDM100

Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)

The following errata may apply to this: BDE70

Retired load uop whose Data Source was: Remote cache HITM

The following errata may apply to this: BDE70

Retired load uop whose Data Source was: forwarded from remote cache

The following errata may apply to this: BDE70

Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
This event counts Demand Data Read requests that access L2 cache, including rejects.
This event counts Read for Ownership (RFO) requests that access L2 cache.
This event counts the number of L2 cache accesses when fetching instructions.
This event counts L2 or L3 HW prefetches that access L2 cache including rejects.
This event counts L1D writebacks that access L2 cache.
This event counts L2 fill requests that access L2 cache.
This event counts L2 writebacks that access L2 cache.
This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.
This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.
This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.
This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.
This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.
Clean L2 cache lines evicted by demand.
This event counts the number of split locks in the super queue.

cpc(3CPC)

https://download.01.org/perfmon/index/

June 18, 2018 OmniOS