AMD_F19H_ZEN4_EVENTS(3CPC) CPU Performance Counters Library Functions AMD_F19H_ZEN4_EVENTS(3CPC)

amd_f19h_zen4_events — AMD Family 19h Zen4 processor performance monitoring events

This manual page describes events specfic to AMD Family 19h Zen4 processors. For more information, please consult the appropriate AMD BIOS and Kernel Developer's guide or Open-Source Register Reference.

Each of the events listed below includes the AMD mnemonic which matches the name found in the AMD manual and a brief summary of the event. If available, a more detailed description of the event follows and then any additional unit values that modify the event. Each unit can be combined to create a new event in the system by placing the '.' character between the event name and the unit name.

The following events are supported:

Retired x87 FP Ops

The number of x87 floating-point Ops that have retired.

This event has the following units which may be used to modify the behavior of the event:

Divide and square root Ops.
Multiply Ops.
Add/subtract Ops.
Retired SSE/AVX FLOPs

This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.13.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.

This event has the following units which may be used to modify the behavior of the event:

bfloat Multiply-Accumulate FLOPs. Each bfloat MAC operation is counted as 2 FLOPS.
Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This event does not include bfloat MAC operations.
Divide/square root FLOPs.
Multiply FLOPs.
Add/subtract FLOPs.
Retired Serializing Ops

The number of serializing Ops retired.

This event has the following units which may be used to modify the behavior of the event:

SSE/AVX bottom-executing ops retired.
SSE/AVX control word mispredict traps.
x87 bottom-executing ops retired.
x87 control word mispredict traps due to mispredictions in RC or PC, or changes in Exception Mask bits.
Retired FP Ops By Width

This event has the following units which may be used to modify the behavior of the event:

Number of packed 512-bit ops retired.
Number of packed 256-bit ops retired.
Number of packed 128-bit ops retired.
Number of scalar ops retired.
Number of MMX ops retired.
Number of x87 ops retired.
Retired FP Ops By Type

Note: Shuffle op counts may count for instructions that are not necessarily thought of as including shuffles. For example, Horizontal Add, Dot Product, and certain MOV instructions may include or use only shuffle type ops.

INT Ops Retired

Note: Shuffle op counts may count for instructions that are not necessarily thought of as including shuffles. For example, Horizontal Add, Dot Product, and certain MOV instructions may include or use only shuffle type ops.

Packed FP Ops Retired

Note: Shuffle op counts may count for instructions that are not necessarily thought of as including shuffles. For example, Horizontal Add, Dot Product, and certain MOV instructions may include or use only shuffle type ops.

Packed INT Ops Retired

Note: Shuffle op counts may count for instructions that are not necessarily thought of as including shuffles. For example, Horizontal Add, Dot Product, and certain MOV instructions may include or use only shuffle type ops. This event also counts FP data type packed and scalar MOV and shuffle.

FP Dispatch Faults

Floating-point Dispatch Faults.

This event has the following units which may be used to modify the behavior of the event:

YMM Spill fault.
YMM Fill fault.
XMM Fill fault.
x87 Fill fault.
Bad Status 2

This event has the following units which may be used to modify the behavior of the event:

Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.
Retired Lock Instructions

This event has the following units which may be used to modify the behavior of the event:

Comparable to legacy bus lock.
Retired CLFLUSH Instructions

The number of retired CLFLUSH instructions. This is a non-speculative event.

Retired CPUID Instructions

The number of CPUID instructions retired.

LS Dispatch

Counts the number of operations dispatched to the LS unit. Unit Masks events are ADDed.

SMIs Received

Counts the number of SMIs received.

Interrupts Taken

Counts the number of interrupts taken.

This event has the following units which may be used to modify the behavior of the event:

Number of Interrupts taken. This event is also counted when UnitMask[7:0]=0.
Store to Load Forward

Number of STLF hits.

Store Commit Cancels 2

This event has the following units which may be used to modify the behavior of the event:

A non-cacheable store and the non-cacheable commit buffer is full.
LS MAB Allocates by Type

Counts when a LS pipe allocates a MAB entry.

Demand Data Cache Fills by Data Source

Demand Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

Requests that return from Extension Memory.
Requests that target another NUMA node and return from DRAM or MMIO from another NUMA node, either from the same or different socket.
Requests that return from another CCX cache in a different NUMA node.
Requests that target the same NUMA node and return from either DRAM or MMIO in the same NUMA node.
Requests that return from another CCX cache in the same NUMA node.
Data returned from L3 or different L2 in the same CCX.
Data returned from the local L2.
Any Data Cache Fills by Data Source

Any Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

Requests that return from Extension Memory.
Requests that target another NUMA node and return from DRAM or MMIO from another NUMA node, either from the same or different socket.
Requests that return from another CCX cache in a different NUMA node.
Requests that target the same NUMA node and return from either DRAM or MMIO in the same NUMA node.
Requests that return from another CCX cache in the same NUMA node.
Data returned from L3 or different L2 in the same CCX.
Data returned from the local L2.
L1 DTLB Misses

This event has the following units which may be used to modify the behavior of the event:

DTLB reload to a 1-G page that also missed in the L2 TLB.
DTLB reload to a 2-M page that also missed in the L2 TLB.
DTLB reload to a coalesced page that also missed in the L2 TLB.
DTLB reload to a 4-K page that missed the L2 TLB.
DTLB reload to a 1-G page that hit in the L2 TLB.
DTLB reload to a 2-M page that hit in the L2 TLB.
DTLB reload to a coalesced page that hit in the L2 TLB.
DTLB reload to a 4-K page that hit in the L2 TLB.
Misaligned loads

This event has the following units which may be used to modify the behavior of the event:

The number of 4-KB misaligned (i.e., page crossing) loads.
The number of 64-B misaligned (i.e., cacheline crossing) loads.
Prefetch Instructions Dispatched

Software Prefetch Instructions Dispatched (Speculative).

This event has the following units which may be used to modify the behavior of the event:

PrefetchNTA instruction. See docAPM3 PREFETCHlevel.
PrefetchW instruction. See docAPM3 PREFETCHW.
PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.
Write Combine Buffer Close Flush

UnitMask events ADDed. Multible WCB can report events at the same time.

Ineffective Software Prefetches

The number of software prefetches that did not fetch data outside of the processor core.

This event has the following units which may be used to modify the behavior of the event:

Software PREFETCH instruction saw a match on an already-allocated miss request buffer.
Software PREFETCH instruction saw a DC hit.
Software Prefetch Data Cache Fills

Software Prefetch Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

Requests that return from Extension Memory.
Requests that target another NUMA node and return from DRAM or MMIO from another NUMA node, either from the same or different socket.
Requests that return from another CCX cache in a different NUMA node.
Requests that target the same NUMA node and return from either DRAM or MMIO in the same NUMA node.
Requests that return from another CCX cache in the same NUMA node.
Data returned from L3 or different L2 in the same CCX.
Data returned from the local L2.
Hardware Prefetch Data Cache Fills

Hardware Prefetch Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

Requests that return from Extension Memory.
Requests that target another NUMA node and return from DRAM or MMIO from another NUMA node, either from the same or different socket.
Requests that return from another CCX cache in a different NUMA node.
Requests that target the same NUMA node and return from either DRAM or MMIO in the same NUMA node.
Requests that return from another CCX cache in the same NUMA node.
Data returned from L3 or different L2 in the same CCX.
Data returned from the local L2.
Count of Allocated Mabs

This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) each cycle.

Cycles not in Halt
All TLB Flushes
P0 Freq Cycles not in Halt

This event has the following units which may be used to modify the behavior of the event:

Counts at the P0 frequency (same as Core::X86::Msr::MPERF) when not in Halt.
Instruction Cache Refills from L2

The number of 64-byte instruction cache lines fulfilled from the L2 cache.

Instruction Cache Refills from System

The number of 64-byte instruction cache line fulfilled from system memory or another cache.

L1 ITLB Miss, L2 ITLB Hit

The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.

ITLB Reload from Page-Table walk

The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses.

This event has the following units which may be used to modify the behavior of the event:

Walk for >4-K Coalesced page.
Walk for 1-G page.
Walk for 2-M page.
Walk to 4-K page.
L2 Branch Prediction Overrides Existing Prediction (speculative)
Dynamic Indirect Predictions

The number of times a branch used the indirect predictor to make a prediction.

Decode Redirects

The number of times the instruction decoder overrides the predicted target.

L1 TLB Hits for Instruction Fetch

The number of instruction fetches that hit in the L1 ITLB.

This event has the following units which may be used to modify the behavior of the event:

L1 Instruction TLB hit (1-G page size).
L1 Instruction TLB hit (2-M page size).
L1 Instruction TLB hit (4-K or 16-K page size).
Resyncs

Counts the number of HW resyncs (pipeline restarts) or NC redirects. NC redirects occur when the front-end transitions to fetching from UC (un-cacheable) memory.

IC Tag Hit/Miss Events

Counts various IC tag related hit and miss events.

Op Cache Hit/Miss

Counts Op Cache micro-tag hit/miss events.

Op Queue Empty

Cycles where the Op Queue is empty.

Source of Op Dispatched From Decoder

Counts the number of ops dispatched from the decoder classified by op source.

This event has the following units which may be used to modify the behavior of the event:

Count of ops dispatched from Loop Buffer.
Count of ops fetched from Op Cache and dispatched.
Count of ops fetched from Instruction Cache and dispatched.
Types of Ops Dispatched From Decoder

Counts the number of ops dispatched from the decoder classified by op type. The UnitMask value encodes which types of ops are counted.

Dispatch Resource Stall Cycles 1

Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. UnitMask bits select the stall types included in the count.

This event has the following units which may be used to modify the behavior of the event:

Counts FP Flush Recovery stall cycles.
Counts FP Scheduler token stall cycles.
Counts FP Register File token stall cycles. This applies to all ops that have an FP or SIMD destination register.
Counts Taken Branch Buffer token stall cycles.
Store Queue resource stall. Counts Store Queue token stall cycles.
Load Queue resource stall. Counts Load Queue token stall cycles.
Integer Physical Register File resource stall. Counts Integer PRF token stall cycles. This applies to all ops that have an integer destination register.
Dynamic Tokens Dispatch Stall Cycles 2

Cycles where a dispatch group is valid but does not get dispatched due to a token stall. UnitMask bits select the stall types included in the count.

This event has the following units which may be used to modify the behavior of the event:

Counts Retire Queue token stall cycles.
Counts Integer Scheduler Queue 3 token stall cycles.
Counts Integer Scheduler Queue 2 token stall cycles.
Counts Integer Scheduler Queue 1 token stall cycles.
Counts Integer Scheduler Queue 0 token stall cycles.
Dispatch Stalls Per Slot

Counts the number of dispatch slots (each cycle) that remained unused for reasons selected by StallReason.

Dispatch Additional Resource Stalls

This PMC event counts additional resource stalls that are not captured by Core::X86::Pmc::Core::DeDisDispatchTokenStalls1 or Core::X86::Pmc::Core::DeDisDispatchTokenStalls2.

Retired Instructions

The number of instructions retired.

Retired Ops

The number of macro-ops retired.

Retired Branch Instructions

The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.

Retired Branch Instructions Mispredicted

The number of retired branch instructions, that were mispredicted.

Retired Taken Branch Instructions

The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.

Retired Taken Branch Instructions Mispredicted

The number of retired taken branch instructions that were mispredicted.

Retired Far Control Transfers

The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.

Retired Near Returns

The number of near return instructions (RET or RET Iw) retired.

Retired Near Returns Mispredicted

The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction.

Retired Indirect Branch Instructions Mispredicted

The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted.

Retired MMX/FP Instructions

The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non- numeric instructions it is not suitable for measuring MFLOPs.

This event has the following units which may be used to modify the behavior of the event:

SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).
MMX instructions.
x87 instructions.
Retired Indirect Branch Instructions

The number of indirect branches retired.

Retired Conditional Branch Instructions
Div Cycles Busy count
Div Op Count
Cycles With No Retire

This event counts cycles when the hardware thread does not retire any ops for reasons selected by UnitMask[4:0]. UnitMask events [4:0] are mutually exclusive. If multiple reasons apply for a given cycle, the lowest numbered UnitMask event is counted.

Retired Microcoded Instructions

Retired Microcoded Instructions.

Retired Microcode Ops

The number of microcode ops that have retired.

Retired Mispredicted Branch Instructions due to Direction Mismatch

The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch.

Retired Unconditional Indirect Branch Instructions Mispredicted

The number of retired unconditional indirect branch instructions that were mispredicted.

Retired Unconditional Branch Instructions

The number of retired unconditional branch instructions.

Tagged IBS Ops

Counts Op IBS related events.

This event has the following units which may be used to modify the behavior of the event:

Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.
Number of Ops tagged by IBS that retired.
Number of Ops tagged by IBS.
Retired Fused Instructions

Counts retired fused instructions.

Requests to L2 Group1

All L2 Cache Requests (Breakdown 1 - Common)

This event has the following units which may be used to modify the behavior of the event:

Data Cache Reads (including hardware and software prefetch).
Data Cache Stores.
Data Cache Shared Reads.
Instruction Cache Reads.
Data Cache State Change Requests. Request change to writable, check L2 for current state.
 
L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event
MiscRequests. Various Noncacheable requests. Non-cached Data Reads, Non- cached Instruction Reads, Self-modifying code checks.
Core to L2 Cacheable Request Access Status

L2 Cache Request Outcomes (not including L2 Prefetch).

This event has the following units which may be used to modify the behavior of the event:

Data Cache Shared Read Hit in L2.
Data Cache Read Hit in L2.
Data Cache Read Hit Non-Modifiable Line in L2.
Data Cache Store or State Change Hit in L2.
Data Cache Req Miss in L2.
Instruction Cache Hit Modifiable Line in L2.
Instruction Cache Hit Non-Modifiable Line in L2.
Instruction Cache Req Miss in L2.
L2 Prefetch Hit in L2

Counts all L2 prefetches accepted by L2 pipeline which hit in the L2 cache.

This event has the following units which may be used to modify the behavior of the event:

L1Region
L1Stride
L1Stream
L2Stride
L2Burst
L2 Up/Down
L2NextLine
L2Stream
L2 Prefetcher Hits in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.

This event has the following units which may be used to modify the behavior of the event:

L1Region
L1Stride
L1Stream
L2Stride
L2Burst
L2 Up/Down
L2NextLine
L2Stream
L2 Prefetcher Misses in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches

This event has the following units which may be used to modify the behavior of the event:

L1Region
L1Stride
L1Stream
L2Stride
L2Burst
L2 Up/Down
L2NextLine
L2Stream

cpc(3CPC)

March 25, 2019 OmniOS