AMD_F17H_ZEN2_EVENTS(3CPC) CPU Performance Counters Library Functions AMD_F17H_ZEN2_EVENTS(3CPC)

amd_f17h_zen2_events — AMD Family 17h Zen2 processor performance monitoring events

This manual page describes events specfic to AMD Family 17h Zen2 processors. For more information, please consult the appropriate AMD BIOS and Kernel Developer's guide or Open-Source Register Reference.

Each of the events listed below includes the AMD mnemonic which matches the name found in the AMD manual and a brief summary of the event. If available, a more detailed description of the event follows and then any additional unit values that modify the event. Each unit can be combined to create a new event in the system by placing the '.' character between the event name and the unit name.

The following events are supported:

Retired SSE/AVX FLOPs

This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event is a MergeEvent since it can count above 15.

This event has the following units which may be used to modify the behavior of the event:

MacFLOPs count as 2 FLOPs. Does not provide a useful count without use of the MergeEvent feature.
Divide/square root FLOPs. Does not provide a useful count without use of the MergeEvent feature.
Multiply FLOPs. Does not provide a useful count without use of the MergeEvent feature.
Add/subtract FLOPs. Does not provide a useful count without use of the MergeEvent feature.
Retired Serializing Ops

The number of serializing Ops retired.

This event has the following units which may be used to modify the behavior of the event:

SSE bottom-executing uOps retired.
SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits.
x87 bottom-executing uOps retired.
x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits.
FP Dispatch Faults

Floating Point Dispatch Faults.

This event has the following units which may be used to modify the behavior of the event:

YMM Spill fault.
YMM Fill fault.
XMM Fill fault.
x87 Fill fault.
Bad Status 2

Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason. There are a number of reasons why this occurs, and this perfmon organizes them into three major groups.

This event has the following units which may be used to modify the behavior of the event:

Non-forwardable conflict; used to reduce STLI's via software. All reasons. The most common among these is that there is only a partial overlap between the store and the load, for example there's an 8B store to address A and a 16B load starting at address A. STLF can't be performed in this case because only some of the load's data is coming from the store, so the load gets StliOther. Another StliOther case is if the load hits a non-cacheable store that's sitting in the non-cacheable buffers (WCBs).
Retired Lock Instructions
Retired CLFLUSH Instructions

The number of retired CLFLUSH instructions. This is a non-speculative event.

Retired CPUID Instructions

The number of CPUID instructions retired.

LS Dispatch

Counts the number of operations dispatched to the LS unit.

SMIs Received

Counts the number of SMIs received.

Interrupts Taken

Counts the number of interrupts taken.

Time Stamp Counter Reads

Counts the number of reads of the TSC (RDTSC instructions). The count is speculative.

Store to Load Forward

Number of STLF hits.

Store Commit Cancels 2

This event has the following units which may be used to modify the behavior of the event:

A non-cacheable store and the non-cacheable commit buffer is full.
Data Cache Accesses

The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event.

DC Miss By Type

This event has the following units which may be used to modify the behavior of the event:

 
 
 
Data Cache Refills from System

Demand Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

DRAM or IO from different die.
Hit in cache; Remote CCX and the address's Home Node is on a different die.
DRAM or IO from this thread's die.
Hit in cache; local CCX (not Local L2), or Remote CCXand the address's Home Node is on this thread's die.
Local L2 hit.
L1 DTLB Miss

This event has the following units which may be used to modify the behavior of the event:

DTLB reload to a 1G page that miss in the L2 TLB.
DTLB reload to a 2M page that miss in the L2 TLB.
 
DTLB reload to a 4K page that miss the L2 TLB.
DTLB reload to a 1G page that hit in the L2 TLB.
DTLB reload to a 2M page that hit in the L2 TLB.
 
DTLB reload to a 4K page that hit in the L2 TLB.
Misaligned loads
Prefetch Instructions Dispatched

Software Prefetch Instructions Dispatched (Speculative).

This event has the following units which may be used to modify the behavior of the event:

PrefetchNTA instruction. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel.
PrefetchW instruction. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel.
PrefetchT0, T1 and T2 instructions. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel.
Ineffective Software Prefetches

The number of software prefetches that did not fetch data outside of the processor core.

This event has the following units which may be used to modify the behavior of the event:

Software PREFETCH instruction saw a match on an already-allocated miss request buffer.
Software PREFETCH instruction saw a DC hit.
Software Prefetch Data Cache Fills

Software Prefetch Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

DRAM or IO from different die.
Hit in cache; Remote CCX and the address's Home Node is on a different die.
DRAM or IO from this thread's die.
Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.
Local L2 hit.
Hardware Prefetch Data Cache Fills

Hardware Prefetch Data Cache Fills by Data Source.

This event has the following units which may be used to modify the behavior of the event:

DRAM or IO from different die.
Hit in cache; Remote CCX and the address's Home Nodeis on a different die.
DRAM or IO from this thread's die.
Hit in cache; local CCX (not Local L2), or Remote CCXand the address's Home Node is on this thread's die.
Local L2 hit.
Cycles not in Halt
All TLB Flushes
Instruction Cache Refills from L2

The number of 64 byte instruction cache line was fulfilled from the L2 cache.

Instruction Cache Refills from System

The number of 64 byte instruction cache line fulfilled from system memory or another cache.

L1 ITLB Miss, L2 ITLB Hit

The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.

L1 ITLB Miss, L2 ITLB Miss

The number of instruction fetches that miss in both the L1 and L2 TLBs.

This event has the following units which may be used to modify the behavior of the event:

Instruction fetches to a 1 GB page.
Instruction fetches to a 2 MB page.
Instruction fetches to a 4 KB page.
L1 Branch Prediction Overrides Existing Prediction (speculative)
L2 Branch Prediction Overrides Existing Prediction (speculative)
Dynamic Indirect Predictions

Indirect Branch Prediction for potential multi-target branch (speculative)

Decoder Overrides Existing Branch Prediction (speculative)
ITLB Instruction Fetch Hits

The number of instruction fetches that hit in the L1 ITLB.

This event has the following units which may be used to modify the behavior of the event:

Instruction fetches to a 1 GB page.
Instruction fetches to a 2 MB page.
Instruction fetches to a 4 KB page.
Micro-Op Queue Empty

Cycles where the Micro-Op Queue is empty.

UOps Dispatched From Decoder

Ops dispatched from either the decoders, OpCache or both.

This event has the following units which may be used to modify the behavior of the event:

Count of dispatched Ops from OpCache.
Count of dispatched Ops from Decoder.
Dispatch Resource Stall Cycles 1

Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.

This event has the following units which may be used to modify the behavior of the event:

FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops.
FP scheduler resource stall. Applies to ops that use the FP scheduler.
floating point register file resource stall. Applies to all FP ops that have a destination register.
taken branch buffer resource stall.
Integer Scheduler miscellaneous resource stall.
Store Queue resource stall. Applies to all ops with store semantics.
Load Queue resource stall. Applies to all ops with load semantics.
Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register.
Dispatch Resource Stall Cycles 0

Cycles where a dispatch group is valid but does not get dispatched due to a token stall.

This event has the following units which may be used to modify the behavior of the event:

SC AGU dispatch stall.
RETIRE Tokens unavailable.
AGSQ Tokens unavailable.
ALU tokens total unavailable.
 
ALSQ 2 Resources unavailable.
ALSQ 1 Resources unavailable.
Retired Instructions
Retired Uops

The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8.

Retired Branch Instructions

The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.

Retired Branch Instructions Mispredicted

The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts).

Retired Taken Branch Instructions

The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.

Retired Taken Branch Instructions Mispredicted

The number of retired taken branch instructions that were mispredicted.

Retired Far Control Transfers

The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.

Retired Near Returns

The number of near return instructions (RET or RET Iw) retired.

Retired Near Returns Mispredicted

The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredictincurs the same penalty as a mispredicted conditional branch instruction.

Retired Indirect Branch Instructions Mispredicted

The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted.

Retired MMX/FP Instructions

The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPs.

This event has the following units which may be used to modify the behavior of the event:

SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).
MMX instructions.
x87 instructions.
Retired Conditional Branch Instructions
Div Cycles Busy count
Div Op Count
Tagged IBS Ops

This event has the following units which may be used to modify the behavior of the event:

Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.
Number of Ops tagged by IBS that retired.
Number of Ops tagged by IBS.
Retired Fused Branch Instructions

The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8.

Requests to L2 Group1

All L2 Cache Requests (Breakdown 1 - Common).

This event has the following units which may be used to modify the behavior of the event:

Data Cache Reads (including hardware and software prefetch).
Data Cache Stores.
Data Cache Shared Reads.
Instruction Cache Reads.
Data Cache State Change Requests. Request change to writable, check L2 for current state.
 
L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.
Miscellaneous events covered in more detail by Core::X86::Pmc::Core::L2RequestG2 (PMCx061).
Requests to L2 Group2

All L2 Cache Requests (Breakdown 2 - Rare).

This event has the following units which may be used to modify the behavior of the event:

Miscellaneous events covered in more detail by Core::X86::Pmc::Core::L2RequestG1 (PMCx060).
Data cache read sized.
Data cache read sized non-cacheable.
Instruction cache read sized.
Instruction cache read sized non-cacheable.
Self-modifying code invalidates.
Bus locks.
Bus Lock Response.
Core to L2 Cacheable Request Access Status

L2 Cache Request Outcomes (not including L2 Prefetch).

This event has the following units which may be used to modify the behavior of the event:

Data Cache Shared Read Hit in L2.
Data Cache Read Hit in L2.
Data Cache Read Hit on Shared Line in L2.
Data Cache Store or State Change Hit in L2.
Data Cache Req Miss in L2 (all types).
Instruction Cache Hit Modifiable Line in L2.
Instruction Cache Hit Clean Line in L2.
Instruction Cache Req Miss in L2.
L2 Prefetch Hit in L2
L2 Prefetcher Hits in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.

L2 Prefetcher Misses in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.

cpc(3CPC)

March 25, 2019 OmniOS